It is possible to make variable length shift registers with large MUXes, though this could consume a lot of logic resources. If you aren't using Xilinx FPGAs, then it might be advisable to look at the programming manuals to figure out what sort of shift register features are supported. With a bit of additional logic it should be possible to implement this with fewer registers, though there could be some disruption when changing the tap selection under certain conditions. What I would recommend is using 6 of these 32-bit shift registers as three 63-bit registers in parallel, one fixed at 63 bits and the other two for the variable taps. If you are using Xilinx FPGAs, the LUTs can be configured as 32-bit shift registers (SR元2), each with one adjustable tap.
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